1. Field of the Invention
The present invention relates to a method for forming semiconductor devices and more particularly, to a method for forming a triple well consisting of three ion-implanted regions, each of which contains only one conductivity type of impurities.
2. Description of the Prior Art
In general, the conventional semiconductor devices are formed by the COOS(Complementary MOS) technology. According to the CMOS technology, a PMOS and an NMOS transistors are fabricated on a same wafer. Accordingly, the well formation technique is required to isolate the transistors from one another.
The diffusion process has been used in the well formation technique. According to this diffusion well formation technique, impurities are implanted at a low energy level and the high-temperature process is performed for a long time. Accordingly, the manufacturing cost is increased and it is difficult to control the characteristics of semiconductor devices because the ion concentration is monotonously decreased from the surface of the well to the bottom of the well.
A conventional well formation technique is developed to solve the above mentioned problems. According to the conventional well formation technique, impurities are implanted at a high energy level and a relatively simple thermal treatment is performed. It is possible to prevent the punch through and the latch up phenomena and to improve the characteristics of semiconductor devices.
The well structure is classified into twin well and triple well structures on the basis of the number of wells. FIG. 1 and FIG. 2 are schematic views of twin well and triple well structures respectively formed on the semiconductor substrate 10 and 20. The twin well includes an n-well 11 and a p-well 12. The triple well, shown in FIG. 2, is formed on the p-type semiconductor substrate 20 and it includes an n-well A, a first p-well B and a second p-well C. The first p-well B is apart, by a predetermined distance, from a second p-well C and is adjacent to the n-well A. The second p-well C is surrounded by the n-well A. The conductivity types of respective wells may be changed into the opposite types when the triple well is formed on the n-type semiconductor substrate.
In comparison with the twin well structure, the triple well structure has an advantage in that it is possible to differently control the characteristics of an NMOS transistor formed on the first p-well B and an NMOS transistor formed on the second p-well C. The triple well structure also has another advantage that the second p-well C has the sufficient voltage to withstand the noise because the well junction capacitance between the second p-well C and the n-well A is relatively large.
The conventional method for forming a triple well is shown in FIGS. 3A to 3D.
First, referring to FIG. 3A, a photoresist pattern 31 is formed on a p-type semiconductor substrate 30. The photoresist pattern 31 exposes two regions, in which an n-well A and a second p-well C are respectively to be formed. The second p-well C is surrounded by the n-well A. After forming the photoresist pattern 31, the implantation processes are carried out by three or four times with different energy to form n-type impurities doped regions 32 in the n-well A and the second p-well C.
Referring to FIG. 3B, the photoresist pattern 31 is removed and a photoresist pattern 33 is formed. The photoresist pattern 33 exposes a region, in which a first p-well B is to be formed. The first p-well B is apart, by a predetermined distance, from the second p-well C and is adjacent to the n-well A. After forming the photoresist pattern 33, the implantation process are carried out by three or four times with different energy to form p-type impurities doped regions 34 in the first p-well B.
Referring next to FIG. 3C, the photoresist pattern 33 is removed and a photoresist pattern 35 is formed. The photoresist pattern 35 exposes a region, in which the second p-well C, surrounded by the n-well, is to be formed. After forming the photoresist pattern 35, the implantation processes are carried out by three or four times with different energy to form p-type impurities doped regions 36 in the second p-well C.
A portion of n-type impurities doped regions 32 was formed in the second p-well C before the p-type impurities doped regions 36 are formed. Accordingly, the amount of the p-type impurities implanted into the second p-well C should be sufficient to offset the n-type impurities formerly implanted into the second p-well C. Therefore, it is difficult to control the doping profile of the second p-well C. The leakage current increases because the substrate is damaged. The mobility of carriers decreases because two conductivity types of ions exist in one well.
Referring next to FIG. 3D, the triple well, which includes the n-well A, the first p-well B and the second p-well C, is formed in the semiconductor substrate 30 by the thermal treatment performed after the implantation processes.
FIG. 4 is an ion concentration profile 41 of the region taken along the line X-X' in FIG. 3D. The ion concentration profile 42 of the n-type impurities implanted in the process to form the n-well A and the ion concentration profile 43 of p-type impurities implanted in the process to form the second p-well C are also shown in FIG. 4. The longitudinal axis represents the logarithm of the effective concentration. The effective concentration is defined by the difference between the p-type impurities concentration Na and the n-type impurities concentration Nd. The ion concentration profile 41 of the second p-well C is determined by the composition of the ion concentration profiles 42 and 43.